Delay lock loop (DLL) circuits and phase lock loop (PLL) circuits are used to generate a periodic signal such as a clock signal based on a periodic reference signal from, for example, an oscillator. The generated clock signal should maintain a specific phase relationship with the reference signal to be synchronized. A DLL circuit or a PLL circuit will adjust the phase of the generated clock signal to maintain the desired phase relationship. DLL and PLL circuits are used, for example, in high-speed clocked memories such as synchronous dynamic random access memory (SDRAM) devices.
Jitter, noise, and other factors sometimes interfere with the operation of DLL and PLL circuitry, so that the desired degree of synchronization is not maintained. Thus, there is a need for improved apparatus, systems, and methods to improve periodic signal synchronization in various electronic devices.